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Philips Semiconductors
256 × 8-bit static low-voltage RAM with
I 2 C-bus interface
Product speci?cation
PCF8570
8.5
I 2 C-bus protocol
Before any data is transmitted on the I 2 C-bus, the device which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the start procedure. The I 2 C-bus configuration for the different
PCF8570 WRITE and READ cycles is shown in Figs 7, 8 and 9.
handbook, full pagewidth
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S
SLAVE ADDRESS
0 A
WORD ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory word address
MBD822
Fig.7 Master transmits to slave receiver (WRITE) mode.
handbook, full pagewidth
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from master
S
SLAVE ADDRESS
0 A
WORD ADDRESS
A
S
SLAVE ADDRESS
1 A
DATA
A
R/W
at this moment master -
transmitter becomes
R/W
n bytes
auto increment
master - receiver and
memory word address
PCF8570 slave -
receiver becomes
slave - transmitter
no acknowledgement
from master
DATA
last byte
1
P
MLB930
auto increment
memory word address
Fig.8 Master reads after setting word address (WRITE word address; READ data).
1999 Jan 06
7
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